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description the CXA3106Q is a pll ic for lcd monitors/ projectors with built-in phase detector, charge pump, vco and counter. the various internal settings are performed by serial data via a 3-line bus. applicable lcd monitor/projector resolution are vga, svga and xga, etc. features supply voltage: 5v 10% single power supply package: 48-pin qfp power consumption: 335mw sync input frequency: 10 to 100khz clock output signal frequency: 10 to 120mhz clock delay: 1/16 to 20/16 clk sync delay: 1/16 to 20/16 clk i/o level: ttl, pecl (complementary) low clock jitter 1/2 clock output pin configuration (top view) functions phase detector enable unlock output output ttl disable function power save function (2 steps) applications crt displays lcd projectors lcd monitors multi-media ?1 CXA3106Q e97447a7x-ps pll ic for lcd monitor/projector sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin qfp (plastic) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 iov cc iognd vcoh vcol vco hold synch syncl sync senable sclk sdata peclv cc vbb dsynch dsyncl clkh clkl clk/2h peclv cc iognd ttlv cc ttlgnd irv cc irgnd rc1 rc2 iref vcohgnd vcognd vcov cc pllgnd pllv cc iov cc iognd tload cs serout divout unlock dv cc dgnd clk/2 clkn clk dsync clk/2l clk/2n 1 2 3 4 5 6 7 8 9 10 11 12
?2 CXA3106Q absolute maximum ratings (ta = 25?) supply voltage iov cc , dv cc , ttlv cc , peclv cc , pllv cc , vcov cc , irv cc , ?.5 to +7.0 v iognd, dgnd, ttlgnd, vcohgnd, pllgnd, vcognd, irgnd ?.5 to +0.5 v input voltage vcoh, vcol, synch, syncl, vco, hold, sync, senable, sclk, sdata, tload, cs iognd ?0.5 to iov cc + 0.5 v rc2 irgnd ?0.5 to irv cc + 0.5 v output current serout, divout, unlock, clk/2n, clk/2, clkn, clk, dsync, clk/2l, clk/2h, clkl, clkh, dsynch, dsyncl, vbb ?0 to +30 ma iref, rc1 ? to +2 ma storage temperature tstg ?5 to +150 ? operating ambient temperature ta ?5 to +75 ? allowable power dissipation p d 750 mw recommended operating conditions min. typ. max. supply voltage iov cc , dv cc , ttlv cc , peclv cc , pllv cc , vcov cc , irv cc 4.75 5.00 5.25 v iognd, dgnd, ttlgnd, vcohgnd, pllgnd, vcognd, irgnd ?.05 0 0.05 v digital input din (pecl) * 1 h level iov cc ?1.1 din (pecl) * 1 l level iov cc ?1.5 v din (ttl) * 2 h level 2.0 v din (ttl) * 2 l level 0.8 v sync, synch, syncl input jitter 1.0 ns operating temperature ta ?0 +75 ? * 1 vcoh, vcol, synch, syncl * 2 vco, hold, sync, senable, sclk, sdata, tload, cs
?3 CXA3106Q block diagram ttlout polarity coarse delay ttlout ttlout 1bit on/off 1bit on/off 1bit on/off dsync (ttl) dsync (pecl) clk (ttl) nclk (ttl) clk (pecl) ttlout ttlout 1bit on/off 1bit on/off clk/2 (ttl) nclk/2 (ttl) clk/2 (pecl) pecl on/off div mux vco fine delay charge pump phase detector peclin ttlin peclin ttlin polarity ttlin programmable counter whole chip power save synthesizer power save ttlin ttlout control register dac rset 1/2 2bit 1bit 5bit 2bit 1bit 12bit 1/256 to 1/4096 clk 1/16 to 20/16 clk 1bit 1bit 1bit cs tload divout serout sdata sclk senable iref 1bit 2bit latch logic 1bit on/off 1bit on/off rc2 rc1 vco (ttl) vco (pecl) sync (ttl) sync (pecl) hold (ttl) read out ttlout 1 to 4 clk unlock vbb peclout peclout peclout unlock detect
?4 CXA3106Q pin no. symbol description reference voltage level 1 iov cc digital power supply 5v 2 iognd digital gnd 0v 3 vcoh external vco input pecl 4 vcol external inverted vco input pecl 5 vco external vco input ttl 6 hold phase detector disable signal input ttl 7 synch sync input pecl 8 syncl inverted sync input pecl 9 sync sync input ttl 10 senable control signal (enable) ttl 11 sclk control signal (clock) ttl 12 sdata control signal (data) ttl 13 tload programmable counter test input ttl 14 cs chip select ttl 15 serout register read output ttl 16 divout programmable counter test output ttl 17 unlock unlock signal output ttl 18 dv cc digital power supply 5v 19 dgnd digital gnd 0v 20 clk/2n inverted 1/2 clock output ttl 21 clk/2 1/2 clock output ttl 22 clkn inverted clock output ttl 23 clk clock output ttl 24 dsync delay sync signal output ttl 25 ttlgnd ttl output gnd 0v 26 ttlv cc ttl output power supply 5v 27 iognd digital gnd 0v 28 peclv cc pecl output power supply 5v 29 clk/2l inverted 1/2 clock output pecl 30 clk/2h 1/2 clock output pecl 31 clkl inverted clock output pecl 32 clkh clock output pecl 33 dsyncl delay sync signal output pecl 34 dsynch inverted delay sync signal output pecl 35 vbb pecl reference voltage peclv cc ?1.3v 36 peclv cc pecl output power supply 5v 37 iognd digital gnd 0v 38 iov cc digital power supply 5v 39 pllv cc pll circuit analog power supply 5v 40 pllgnd pll circuit analog gnd 0v 41 vcov cc vco circuit analog power supply 5v 42 vcognd vco circuit analog gnd 0v 43 vcohgnd vco sub analog gnd 0v 44 iref charge pump current preparation 1.3v 45 rc2 external pin for lpf 2.0v to 4.4v 46 rc1 external pin for lpf 2.1v 47 irgnd iref analog gnd 0v 48 irv cc iref analog power supply 5v
?5 CXA3106Q pin description and i/o pin equivalent circuit digital power supply. ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. digital gnd. digital power supply. digital gnd. ttl output gnd. ttl output power supply. ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. digital gnd. pecl output power supply. ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. pecl output power supply. ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. digital gnd. digital power supply. ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. pll circuit analog power supply. ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. pll circuit analog gnd. vco circuit analog power supply. ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. vco circuit analog gnd. vco sub analog gnd. iref analog gnd. iref analog power supply. ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. 1 2 18 19 25 26 27 28 36 37 38 39 40 41 42 43 47 48 iov cc iognd dv cc dgnd ttlgnd ttlv cc iognd peclv cc peclv cc iognd iov cc pllv cc pllgnd vcov cc vcognd vcohgnd irgnd irv cc 5v 0v 5v 0v 0v 5v 0v 5v 5v 0v 5v 5v 0v 5v 0v 0v 0v 5v pin no. symbol i/o reference voltage level equivalent circuit description
?6 CXA3106Q external vco input. programmable counter test input (switchable by a control register). when using the vco pecl input, open the pin 5 vco ttl input. external inverted vco input. when open, this pin goes to the pecl threshold voltage (iovcc ?1.3v). only the pin 3 vcoh input with vcol input open can be also operated but complementary input is recommended in order to realize stable high-speed operation. sync input. when using the synch pecl input, open the pin 9 sync ttl input. the sync signal can be switched between positive/negative polarity by an internal register. inverted sync input. when open, this pin goes to the pecl threshold voltage (iovcc ?1.3v). only the pin 7 synch input with syncl input open can be also operated but complementary input is recommended in order to realize stable high-speed operation. 3 4 7 8 vcoh vcol synch syncl pecl pecl pecl pecl i i i i 3 4 8 7 iov cc iognd r r pin no. symbol i/o reference voltage level equivalent circuit description
?7 CXA3106Q external vco input. programmable counter test input (controlled by a control register). when using the vco ttl input, open the pin 3 vcoh and pin 4 vcol pecl inputs. phase detector disable signal. active high. when this pin is high, the phase detector output is held. this pin goes to high level when open. (see the hold timing chart.) sync input. when using the sync ttl input, open the pin 7 synch and pin 8 syncl pecl inputs. the sync signal can be switched between positive/negative polarity by a control register. control signal (enable) for setting the internal registers. when senable is low, registers can be written; when high, registers can be read. (see the control register table and control timing chart.) control signal (clock) for setting the internal registers. when senable is low, sdata is loaded to the registers at the rising edge of sclk. when senable is high, the register contents are output from serout at the falling edge of sclk. (see the control register table and control timing chart.) control signal (data) for setting the internal registers. (see the control register table and control timing chart.) programmable counter test input. this pin is normally open status and high. register contents can be loaded immediately to programmable counter by setting tload low during the programmable counter test mode. 5 6 9 10 11 12 13 vco hold sync senable sclk sdata tload ttl ttl ttl ttl ttl ttl ttl i i i i i i i 5 6 9 10 12 13 r/2 r 2r 1.5v iov cc iognd 11 pin no. symbol i/o reference voltage level equivalent circuit description
?8 CXA3106Q chip select. when low, all circuits including the register circuit are set to the power save mode. when high, all circuits are set to operating mode. register read output. when senable is high, the register contents are output from serout at the falling edge of sclk. (see the control register timing chart.) ttl output can be turned on/off (high impedance) by a control register. programmable counter test output. (see the i/o timing chart.) ttl output can be turned on/off (high impedance) by a control register. inverted 1/2 clock output. (see the i/o timing chart.) ttl output can be turned on/off (high impedance) by a control register. 1/2 clock output. (see the i/o timing chart.) ttl output can be turned on/off (high impedance) by a control register. inverted clock output. (see the i/o timing chart.) ttl output can be turned on/off (high impedance) by a control register. clock output. (see the i/o timing chart.) ttl output can be turned on/off (high impedance) by a control register. delay sync signal output. (see the i/o timing chart.) ttl output can be turned on/off (high impedance) and switched between positive/negative polarity by a control register. 14 15 16 20 21 22 23 24 cs serout divout clk/2n clk/2 clkn clk dsync ttl ttl ttl ttl ttl ttl ttl ttl i o o o o o o o iov cc iognd 14 iov cc iognd ttlv cc ttlgnd 15 20 21 22 23 24 16 100k pin no. symbol i/o reference voltage level equivalent circuit description
?9 CXA3106Q unlock signal output. this pin is an open collector output, and pulls in the current when a phase difference occurs. the unlock sensitivity can be adjusted by connecting a capacitor and resistors to this output as appropriate. (see the unlock timing chart.) ttl output can be turned on/off (high impedance) by a control register. inverted 1/2 clock output. (see the i/o timing chart.) this pin requires an external pull- down resistor. when not used, connect to peclv cc without connecting a pull-down resistor. 1/2 clock output. (see the i/o timing chart.) this pin requires an external pull- down resistor. when not used, connect to peclv cc without connecting a pull-down resistor. inverted clock output. (see the i/o timing chart.) this pin requires an external pull- down resistor. when not used, connect to peclv cc without connecting a pull-down resistor. clock output. (see the i/o timing chart.) this pin requires an external pull- down resistor. when not used, connect to peclv cc without connecting a pull-down resistor. delay sync signal output. (see the i/o timing chart.) this pin requires an external pull- down resistor. when not used, connect to peclv cc without connecting a pull-down resistor. inverted delay sync signal output. (see the i/o timing chart.) this pin requires an external pull- down resistor. when not used, connect to peclv cc without connecting a pull-down resistor. 17 29 30 31 32 33 34 unlock clk/2l clk/2h clkl clkh dsyncl dsynch ttl pecl pecl pecl pecl pecl pecl o o o o o o o 17 ttlv cc iognd ttlgnd iognd iov cc 29 30 34 31 32 33 peclv cc pin no. symbol i/o reference voltage level equivalent circuit description
?10 CXA3106Q pecl reference voltage. when used, ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. charge pump current preparation. connect to gnd via an external resistor (1.6k ). ground this pin to the ground pattern with a 0.1f ceramic chip capacitor as close to the pin as possible. external pin for lpf. see the recommended operating circuit for the external circuits. note that external resistors and capacitors should be metal film resistors and temperature compensation capacitors which are relatively unaffected by temperature change. external pin for lpf. see the recommended operating circuit for the external circuits. vbb iref rc2 rc1 o o o o peclv cc ?.3v 1.3v 2.0v to 4.4v 2.1v 35 44 45 46 pin no. symbol i/o reference voltage level equivalent circuit description peclv cc iognd 35 irv cc irgnd 44 iognd vcov cc vcognd iognd irgnd irv cc 45 46 100
?11 CXA3106Q control register table register no. register 1 register 2 register 3 register 4 register 5 register 6 register 7 register name register read no divreg1 register read no divreg2 register read no cenfrereg register read no delayreg register read no cpreg register read no ttlpolreg register read no testpowreg data7 msb 1 vco div bit 7 30 unlock enable dat6 2 vco div bit 6 13 div 1, 2, 4 bit 1 20 coarse delay bit 1 31 dsync enable data5 3 vco div bit 5 14 div 1, 2, 4 bit 0 21 coarse delay bit 0 32 nclk/2 enable data4 4 vco div bit 4 15 22 fine delay bit 4 33 clk/2 enable data3 5 vco div bit 3 9 vco div bit 11 16 23 fine delay bit 3 34 nclk enable 38 divout enable data2 6 vco div bit 2 10 vco div bit 10 17 24 fine delay bit 2 27 pd pol 35 clk enable 39 read out power data1 7 vco div bit 1 11 vco div bit 9 18 25 fine delay bit 1 28 c.pump bit 1 36 dsync pol 40 synth power data0 8 vco div bit 0 12 vco div bit 8 19 26 fine delay bit 0 29 c.pump bit 0 37 sync pol 41 vco by-pass addr2 msb 0 0 0 1 1 1 1 addr1 0 1 1 0 0 1 1 addr0 lsb 1 0 1 0 1 0 1 data address
?12 CXA3106Q electrical characteristics (ta = 25?, v cc = 5v, gnd = 0v) ma ma ma v v v ? ? v v ? ? na ns ns v v v v item symbol conditions min. typ. max. unit current consumption (excluding output current) current consumption 1 current consumption 2 current consumption 3 digital input digital high level input voltage (pecl) digital low level input voltage (pecl) vcol, syncl input open voltage (pecl) digital high level input current (pecl) digital low level input current (pecl) digital high level input voltage (ttl) digital low level input voltage (ttl) digital high level input current (ttl) digital low level input current (ttl) hold characteristics rc1 input pin leak current hold signal set-up time hold signal hold time digital output digital high level output voltage (pecl) digital low level output voltage (pecl) pecl output reference voltage digital high level output voltage (ttl) digital low level output voltage (ttl) i cc 1 i cc 2 i cc 3 v ih 1 v il 1 v io i ih 1 i il 1 v ih 2 v il 2 i ih 2 i il 2 ileak ths thh v oh 1 v ol 1 vbb v oh 2 v ol 2 cs = h, synth power = 1 cs = h, synth power = 0 cs = l v ih = iov cc ?0.8v v il = iov cc ?1.6v v ih = 2.7v v il = 0.5v rl = 330 rl = 330 rl = 330 cl = 10pf cl = 10pf 40 5 3 iov cc ?.15 ?00 ?00 2.0 ?00 ?00 20 20 peclv cc ?.1 2.7 67 15 10 iov cc ?.3 peclv cc ?.3 100 30 20 iov cc ?.5 100 0 0.8 ?0 ?00 1.00 peclv cc ?.6 0.5
?13 CXA3106Q unlock output unlock output current sync input sync input frequency range dsync output dsync output variable coarse delay time setting resolution dsync output variable coarse delay time dsync output variable fine delay time setting resolution dsync output variable fine delay time vco characteristics div output frequency operation range 1 div output frequency operation range 2 div output frequency operation range 3 vco lock range vco gain 1 vco gain 2 vco gain 3 charge pump current 1 charge pump current 2 charge pump current 3 vco counter bits div = 1/1 div = 1/2 div = 1/4 div = 1/1 div = 1/2 div = 1/4 c.pump bit = 00, iref = 1.6k c.pump bit = 10, iref = 1.6k c.pump bit = 11, iref = 1.6k ?0 10 1 1/16 40 20 10 2.0 200 100 50 80 350 1350 2 5 320 160 80 100 400 1600 12 100 4 20/16 120 60 30 4.4 550 270 135 130 500 1800 ma khz bit clk bit clk mhz mhz mhz v mrad/sv mrad/sv mrad/sv ? ? ? bit iunlock fin rdsync1 td1 rdsync2 td2 f vco 1 f vco 2 f vco 3 vlock k vco 1 k vco 2 k vco 3 kpd1 kpd2 kpd3 rdiv2 item symbol conditions min. typ. max. unit
?14 CXA3106Q clk (clk, clk/2) output clk output (pecl) frequency range 1 clk output (pecl) frequency range 2 clk output (pecl) frequency range 3 clk, clk/2 output (pecl) rise time clk, clk/2 output (pecl) fall time clk output (ttl) frequency range 1 clk output (ttl) frequency range 2 clk output (ttl) frequency range 3 clk, clk/2 output (ttl) rise time clk, clk/2 output (ttl) fall time clk output (pecl, ttl) duty sync input (pecl) and clk output (pecl) delay offset clk output (pecl) and dsync output (pecl) phase difference clk output (pecl) and clk/2 output (pecl) phase difference clk output (pecl) and divout output (ttl) rise phase difference clk output (pecl) and divout output (ttl) fall phase difference dsync, clk, clk/2 pecl output and ttl output phase difference div = 1/1 div = 1/2 div = 1/4 10% to 90%, rl = 330 10% to 90%, rl = 330 div = 1/1 div = 1/2 div = 1/4 10% to 90%, cl = 10pf 10% to 90%, cl = 10pf cl = 10pf cl = 10pf cl = 10pf cl = 10pf cl = 10pf cl = 10pf cl = 10pf 40 20 10 1.0 1.0 40 20 10 2.0 2.0 40 1.5 0.0 1.5 1.5 1.5 3.0 3.0 50 1 2.4 0.8 14 11 3.0 120 60 30 2.0 2.0 80 60 30 4.0 4.0 60 3.0 1.0 4.5 mhz mhz mhz ns ns mhz mhz mhz ns ns % ns ns ns ns ns ns fclk1pecl fclk2pecl fclk3pecl trpecl tfpecl fclk1ttl fclk2ttl fclk3ttl trttl tfttl dclk2 td3 td4 td5 td6 td7 td8 item symbol conditions min. typ. max. unit
?15 CXA3106Q clk (clk, clk/2) output clk vs. sync output jitter (ntsc) clk vs. sync output jitter (vga) clk vs. sync output jitter (svga) clk vs. sync output jitter (xga) clk vs. dsync output jitter control registers sclk frequency senable setup time senable hold time sdata setup time sdata hold time senable setup time senable hold time triggered at sync fsync = 15.73khz (crystal) fclk = 12.27mhz n = 780 fine delay = 2/16 to 20/16 triggered at sync fsync = 31.47khz (crystal) fclk = 25.18mhz n = 800 triggered at sync fsync = 48.08khz (crystal) fclk = 50.00mhz n = 1040 triggered at sync fsync = 56.48khz (crystal) fclk = 75.00mhz n = 1328 triggered at dsync in write/read mode in write mode in write mode in write mode in read mode in read mode in read mode 3 0 3 0 3 0 4.0 3.0 2.0 1.6 7.0 5.0 3.0 2.5 0.1 12 ns ns ns ns ns mhz ns ns ns ns ns ns tj1p-p tj2p-p tj3p-p tj4p-p tj5p-p sclk tens tenh tds tdh tnens tnenh item symbol conditions min. typ. max. unit
?16 CXA3106Q description of block diagram sync input sync signals in the range of 10 to 100khz can be input. input supports both positive and negative polarity. pecl input can also be a single input. when sync is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal. when sync is negative polarity, the clock is regenerated in synchronization with the falling edge of the sync signal. vco oscillation stops when there is no sync input. register: sync pol sync input polarity 1 positive 0 negative phase detector the phase detector operates at the sync input frequency of 10 to 100khz. the pd input polarity should be set to the default pd pol = 1. phase comparison is performed at the edges. the input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped at the front end of the CXA3106Q when inputting a noisy signal. the phase detector hold signal is supplied by ttl. (see the hold timing chart.) the pll unlock signal is output by an open collector. (see the unlock timing chart.) charge pump the gain (i, i/4, i/16) can be varied by changing the charge pump current using 2 bits of control register. register: c.pump bit 1 register: c.pump bit 0 0 0 1 0 1 1 charge pump current 100a 400a 1600a register: div 1, 2, 4 bit 1 register: div 1, 2, 4 bit 0 0 0 1 0 1 1 counter frequency divisions 1/1 1/2 1/4 lpf this is a loop filter comprised of the external capacitors and resistor. be sure to use metal film resistors with little temperature variation and a temperature-compensated capacitor. in particular, the 0.33f capacitor should be equivalent to murata's high dielectric constant series capacitor type b or better. (electrostatic capacitance change ratio 10%: t = ?5 to +85?) vco the vco oscillator frequency covers from 40 to 120mhz. vco rear-end counter the vco output is frequency divided to 1/1, 1/2 or 1/4 by switching 2 bits of control register. the operating range can be expanded to 10 to 120mhz by combining the counter with a vco frequency divider.
?17 CXA3106Q feedback programmable counter this counter can be set as desired from 256 to 4096 using 12 bits. frequency divisions = (m + 1) 8 + n, n: 3 bits (vco div bits 0 to 2), m: 9 bits (vco div bits 3 to 11) when the register value is changed, the new setting is actually loaded to the counter when the counter value becomes "all 0". clock output when sync input is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal. the clock output delay time can be changed in the range of 1/16 to 20/16 clk using 5 bits of control register. (see the i/o timing chart.) output is ttl and pecl (complementary), and supports both positive and negative polarity. clock ttl output can also be turned off independently. register: clock enable clock output status 1 on 0 off register: clock enable clock output status 1 on 0 off register: dsync pol dsync output polarity 1 positive 0 negative lower delay line fine delay bits 0 to 4 delay time 00000 1/16clk 00001 2/16clk ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 10011 20/16clk upper delay line coarse delay bits 0 to 1 delay time 00 1clk 01 2clk 10 3clk 11 4clk delay sync output the front edge of the delay sync pulse is latched by the pulse obtained by frequency dividing the clk regenerated by the pll, so there is almost no jitter with respect to clk. this front edge can be used as the reset signal for the system timing circuit. the rear edge of the delay sync pulse is latched by the clk regenerated by the pll. this relationship is undefined for one clock as shown in the timing chart. the delay sync output delay time can be varied in two stages. first, the delay time can be varied in the range of 1/16 to 20/16 clk using 5 bits of control register, and then in the range of 1 to 4 clk using 2 bits of control register. in other words, the total delay time is ((1/16 to 20/16) + (1 to 4)) clk. (see the i/o timing chart.) dsync output is ttl and pecl (complementary), and supports both positive and negative polarity. clock ttl output can also be turned off. 1/2 clock output reset is performed at the delay sync timing and the clock output is frequency divided by 1/2. (see the i/o timing chart.) both odd and even output are ttl and pecl output. ttl output can also be turned off independently. register: clock enable clock output status 1 on 0 off
?18 CXA3106Q control circuit (3-bit address, 8-bit data) the timing and input methods are described hereafter. feedback programmable counter control register1, 2 12bit vco rear-end counter control register3 2bit fine delay line control register4 5bit coarse delay line control register4 2bit charge pump current dac control register5 2bit phase detector input positive/negative polarity control register5 1bit sync input positive/negative polarity control register6 1bit delay sync output positive/negative polarity control register6 1bit clock ttl output off function register6 1bit inverted clock ttl output off function register6 1bit 1/2 clock ttl output off function register6 1bit inverted 1/2 clock ttl output off function register6 1bit delay sync ttl output off function register6 1bit unlock output off function register6 1bit programmable counter input switching register7 1bit power save with register contents held register7 1bit register read function power on/off register7 1bit programmable counter ttl output off function register7 1bit power save the CXA3106Q realizes 2-step power saving (all off, control registers only on). this is controlled by a control register and the chip selector. step 1: chip selector control cs power save status h power on l all off register: synth power power save status 1 power on 0 control registers only on step 2: control register control readout circuit (during test mode) the control register contents can be read by serial data from serout. (see the control register timing chart.) register: read out power readout status 0 function off 1 function on
?19 CXA3106Q register: divout enable divout output status 0 off 1 on register: vco by-pass input status 1 internal vco 0 external input tload forced load control status h function off l function on programmable counter output (during test mode) the programmable counter output is ttl output from the divout pin. (see the i/o timing chart.) this output is normally not used. tload input (during test mode) this control signal forcibly loads the control register contents to the programmable counter. this signal is normally not used. vco input (during test mode) this is the programmable counter test signal input pin. this pin can be switched internally by the mux circuit. ttl and pecl input are possible. this pin is normally not used.
?20 CXA3106Q control register timing 1) write mode many CXA3106Q functions can be controlled via a program. characteristics are changed by setting the internal control register values via a serial interface comprised of three pins: senable (pin 10), sclk (pin 11) and sdata (pin 12). the write timing diagram is shown below. input the 8-bit data and 3-bit register address msb first to the sdata pin. some registers are not 8 bits, but the data is input aligned with the lsb side in these cases. (see the register table.) senable is the enable signal and is active low. sclk is the transfer clock signal, and data is loaded to the ic at the rising edge. when senable rises, sclk must be high. (registers are set at the rising edge of senable.) when senable falls, sclk may be either high or low. senable sdata sclk senable sdata sclk data 8bit address 3bit enlarged tens tenh tdh tds enlarged for example, when inputting a 16-bit signal, the initial 5 bits are invalid and the latter 11 bits are valid. this is to say that the latter 11 bits are loaded to the register. senable sdata sclk data 8bit address 3bit invalid data 5bit
?21 CXA3106Q the settings of the frequency divider (2 bits, div1, 2, 4) and programmable counter (12 bits, vcodiv) at the rear end of the vco are transferred in the order shown below. (the data will be set when the three registers are transferred.) first divreg2, cenfrereg and divreg1 are set, and then the data is transferred independently at the timings shown below. divreg2 (upper 4 bits of vcodiv) cenfrereg (2 bits of div1, 2, 4) divreg1 (lower 8 bits of vcodiv) all three of the above registers must be changed even when changing only (2 bits of div1, 2, 4). this is the same when changing only (12 bits of vcodiv). senable sdata sclk divreg2 cenfrereg divreg1
?22 CXA3106Q 2) read mode data can be transferred from the shift register to the data register only when senable is high. binary data can be read from the data register by inputting sclk when senable is high. data is loaded from the data register to the scan path circuit each time one clock is input to sclk, and is output sequentially from the register read no. 1 data (vcodiv bit 7) through the serout pin. when the 41st sclk clock pulse is input, the register read no. 41 data (vco by-pass) is output. then, when the 42nd clock pulse is input to sclk, the output returns to the register read no. 1 data (vcodiv bit 7) and the data output is repeated. also, the data output from the scan path circuit is automatically reloaded even when the shift register data is changed during data output. note) since all registers do not have 8 bits, only the valid bits of each register are loaded to the scan path circuit. (see the control register table for the actual register read no.) serout i/p shift register, 11 bits 8 bit data 3 bit address clk nen tr en clk sclk senable 7 data registers (41 latches). registers are different lengths up to 8 bit scan path, 1 element per register bit tnens tnenh read no. 1 read no. 2 read no. n n 1 2 sena serout sclk block diagram during read mode timing chart during read mode
?23 CXA3106Q timing charts 1. i/o timing 0 1 2 3 4clk td3 (typ. 1ns) 1clk 1/16clk to 20/16clk td2 8clk td7 (typ. 11ns) td6 (typ. 14ns) (1 to 4) clk td1 td4 (typ. 2.4ns) 1clk sync input (positive polarity) (pecl) clk output (pecl) divout output (ttl) dsync output (positive polarity) (pecl) reset (internal signal) clk/2 output (pecl) td5 (typ. 0.8ns)
?24 CXA3106Q 2. hold timing divout output (ttl) sync input (sync pol = 0) clk output hold input (ttl) a aa aa aa a a thh ths thh ths t hold the phase comparison output is held and fixed vco output frequency is output. sync input (sync pol = 1) hold signal set-up time (ths) is a time from the rising edge of hold signal to the falling edge of divout. or, when sync pol = 1, it is a time from the falling edge of hold signal to the rising edge of sync; when sync pol = 0, it is the time from the falling edge of hold signal to the falling edge of sync. hold signal hold time (thh) is the time from the falling edge of divout to falling edge of hold signal. or, when sync pol = 1, it is the time from the rising edge of sync to the rising edge of hold signal; when sync pol = 0, it is the time from the falling edge of sync to the rising edge of hold signal. when the hold input is held, the clk frequency fluctuation can be calculated as follows. vco i i sw sw c ? +q d v i leak d f c ? ? v = q = i leak ?t hold c: loop filter capacitance ? v: voltage variation due to leak current i leak : internal amplifier leak current t hold : hold time ? v = i leak ?t hold /c ? f = ? v ?kvco = i leak ?t hold /c ?kvco for example, assuming f = 100mhz, i leak = 1na, t hold = 1ms, c = 0.33f, and kvco = 2 ?50mhz/v, then: ? v = 1 10 ? ?1 10 ? /(0.33 10 ? ) = 3 10 ? [v] ? f = 1 10 ? ?1 10 ? /(0.33 10 ? ) ?50 10 6 = 151 [hz]
?25 CXA3106Q 3. unlock timing unlock detect unlock v cc signal from phase comparator c r1 r2 s2 i2 i1 s1 outside the ic inside the ic the unlock detect output is an open collector. when unlock detect output s1 goes high, the current i1 is pulled in. the unlock sensitivity can be adjusted by connecting external resistors (r1, r2) and a capacitor (c) to this output pin as appropriate and changing these values. operation during three modes is described below. case 1: when there is no phase difference, that is to say, when the pll is locked. the s1 signal is low and the s2 signal is high. the unlock output remains low. s1 s2 unlock threshold level case 2: when there is a phase difference, that is to say, when the s1 signal goes high and low as shown in the figure below, the fall slew rate of the s2 signal is determined by the current i1 flowing into that open collector. therefore, increasing the resistance r1 causes the s2 signal fall slew rate to become slower. also, since the s2 signal rise slew rate is determined by the current i2, reducing the resistance r2 causes the s2 signal rise slew rate to become faster. if this integrated s2 signal does not fall below the threshold level of the next inverter, the unlock signal stays low, and the pll is said to be locked. s1 s2 unlock threshold level case 3: however, even if a phase difference exists as shown above, if the resistance r1 is reduced, the current i1 flowing into the open collector increases, and the s2 signal fall slew rate becomes faster. also, if the resistance r2 is increased, the s2 signal rise slew rate becomes slower. if this integrated s2 signal falls below the threshold level of the next inverter, the unlock signal goes from low to high, and the pll is said to be unlocked. s1 s2 unlock threshold level
?26 CXA3106Q charge pump and loop filter settings the CXA3106Q's charge pump is a constant-current output type as shown below. s1 s2 to lpf v cc when a constant-current output charge pump circuit is used inside the pll, the phase detector output acts as a current source, and the dimension of its transmittance kpd is a/rad. also, when considering the vco input as a voltage, the lpf transmittance dimension must be expressed in ohms ( = v/a). therefore, the pll transmittance when a constant-current output charge pump circuit is used is as follows. 1/s kpd (a/rad) f (s) ( w ) kvco (rad/s/v) 1/s 1/n pd lpf vco counter q o n w 0 /n w 0 /n q r w r + the pll closed loop transmittance is obtained by the following formula. here, kpd, f (s), and kvco are: kpd: phase comparator gain (a/rad) f (s): loop filter transmittance ( ) kvco: vco gain (rad/s/v) * 1 the reason for the 1/s inside the phase detector is as follows. q o (t)/n = t o w 0 (t)/ndt + q o (t = 0)/n ... (a) q o (t = 0) = 0 q o (t)/n = t o w 0 (t)/ndt ... (b) performing laplace conversion: q o (s)/n = w 0 (s)/n ... (c) 1 s q o/n q r kpd ?f (s) ?kvco 1/n ?1/s 1 + kpd ?f (s) ?kvco 1/n ?1/s = ... (1)
?27 CXA3106Q the loop filter f (s) is described below. the loop filter smoothes the output pulse from the phase comparator and inputs it as the dc component to the vco. in addition to this, however, the loop filter also plays an important element in determining the pll response characteristics. typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. however, the CXA3106Q's lpf is a current input type active filter as shown below, so the following calculations show an actual example of deriving the pll closed loop transmittance when using this type of filter and then using this transmittance to create a formula for setting the filter constants. current input type active filter vo cr i i ?o ? ? the filter transmittance is as follows. + vo = (r + ) f (s) = = \t = rc here, assuming a > 1, then: f (s) = ........................... (2) next, substituting (2) into (1) and obtaining the overall closed loop transmittance for the pll: = ... (3) = ............................................ (4) w n = ...................................................... (5) z = w n t ................................................................. (6) the bode diagram for formula (2) is as follows. log w log w ?5deg 0 ?0 phase [deg] log scale gain [db] 1 t 2 zw ns + w n 2 s 2 + 2 zw ns + w n 2 1 + src sc a 1 + a 1 + s t sc q o/n q r ?s + 1 + s t sc a 1 + a kpd ?kvco ? t nc kpd ?kvco nc ?s + s 2 + kpd ?kvco ? t nc kpd ?kvco nc kpd ?kvco nc vo a 1 sc 1 2
?28 CXA3106Q here, w n and z are as follows. w n characteristic angular frequency: the oscillatory angular frequency when pll oscillation is assumed to have been maintained by the loop filter and individual loop gains is called the characteristic angular frequency: w n. z damping factor: this is the pll transient response characteristic, and serves as a measure of the pll stability. it is determined by the loop gain and the loop filter. a capacitor c2 is added to the actual loop filter. this added capacitor c2 is used to reduce the r noise, and a value of about 1/10 to 1/1000 of c1 should be selected as necessary. current input type active filter with added capacitor c2 vo c2 c1 r i i ?o ? ? the filter transmittance is as follows. f (s) = = .................. (7) t 1 = c1 ?r t 2 = here, assuming c2 = c1/100, then: t 2 = = c1 ?r = t 1 the bode diagram for formula (7) is as follows. 1 t 1 log w log w ?5deg 0 ?0 phase [deg] log scale gain [db] 1 t 2 1 + c1 r ?s s ((c1 + c2) + c1 ?c2 ?r ?s) 1 + t 1 ?s s (c1 + c2) (1 + t 2 ?s) c1 ?c2 ?r c1 + c2 c1 ?c1/100 ?r c1 + c1/100 1 101 1 101
?29 CXA3106Q next, the various parameters inside an actual CXA3106Q are obtained. the CXA3106Q's charge pump output block and the lpf circuit are as follows. s1 s2 to vco v cc c2 c1 r1 100k CXA3106Q 100 20k 100a or 400a or 1600a 100a or 400a or 1600a 45 46 first, kpd is as follows. kpd = 100/2 or 400/2 or 1600/2 (a/rad) typical kvco characteristics curves for the CXA3106Q's internal vco are as follows. 23 4 40 80 120 vco input voltage [v] vco frequency [mhz] vco div = 1/1 vco div = 1/2 vco div = 1/4 therefore, kvco is as follows. kvco = 2 ?50m or 2 ?25m or 2 ?12.5m (rad/s/v)
?30 CXA3106Q w n and z calculated for various types of computer signals are shown below. here, the various parameters are as follows. fsync: input h sync frequency fclk: output clock frequency kpd * 2 : phase comparator gain * 2 (kpd*2 = +100 or 400 or 1600) kvco/2 : vco gain (when vco div = 1/1, kvco/2 = 50) (when vco div = 1/2, kvco/2 = 50/2) (when vco div = 1/4, kvco/2 = 50/4) n: counter value c1: loop filter capacitance value r1: loop filter resistance value ntsc ntsc ntsc pal pal pal pc-98 vga mac vesa svga svga svga svga svga mac xga xga xga mac xga resolution 640 480 640 480 640 480 640 480 800 600 800 600 800 600 800 600 800 600 832 624 1024 768 1024 768 1024 768 1024 768 1024 768 fsync khz 15.734 15.734 15.734 15.625 15.625 15.625 24.82 31.47 35.00 37.86 35.16 37.88 46.88 48.08 53.67 49.72 48.36 56.48 60.02 60.24 68.68 fclk mhz 12.27 18.41 24.55 14.69 22.03 29.38 21.05 25.18 30.24 31.50 36.00 40.00 49.50 50.00 56.25 57.28 65.00 75.00 78.75 80.00 94.50 kpd * 2 ? 400 400 400 400 400 400 100 100 400 400 400 400 400 400 400 400 400 400 400 400 400 n setting 780 1170 1560 940 1410 1880 848 800 864 832 1024 1056 1056 1040 1048 1152 1344 1328 1312 1328 1376 c1 ? 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 r1 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 3300 fn khz 0.70 0.57 0.70 0.64 0.52 0.64 0.48 0.49 0.94 0.96 0.87 0.85 0.85 0.86 0.86 0.82 1.07 1.08 1.08 1.08 1.06 z 2.40 1.96 2.40 2.19 1.78 2.19 1.63 1.68 3.22 3.29 2.96 2.92 2.92 2.94 2.93 2.79 3.66 3.68 3.70 3.68 3.61 c.pump setting bit1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 kvco/2 m/(s * v) 50/4 50/4 50/2 50/4 50/4 50/2 50/2 50/2 50/2 50/2 50/2 50/2 50/2 50/2 50/2 50/2 50/1 50/1 50/1 50/1 50/1 bit0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 div1.2.4 setting bit1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 bit0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w n khzrad 4.41 3.60 4.41 4.01 3.28 4.01 2.99 3.08 5.92 6.04 5.44 5.36 5.36 5.40 5.38 5.13 6.72 6.76 6.80 6.76 6.64
?31 CXA3106Q clk jitter evaluation method the regenerated clk is obtained by applying hsync to the CXA3106Q. apply this clk to a digital oscilloscope and observe the clk waveform using hsync as the trigger. digital oscillo- scope CXA3106Q triger pulse generator ch1 clk hsync h sync back porch front porch active video 15 to 25% of tsync tsync = 1/fsync enlarged enlarged enlarged enlarged clk tjp-p trigger clk hsync computer signal the clk jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in the figure. the clk jitter size varies according to the difference in the relative position with respect to hsync. therefore, when the observation point is changed, the clk jitter at that point is observed. the figure below shows an typical example of the clk jitter for the CXA3106Q. the clk jitter increases slightly at the rising edge of hsync (in the case of positive polarity), and then settles down thereafter. however, this is not a problem as the active pixels start after about 20% of the h cycle has passed from the rising edge of hsync. 0 1/4 ?tsync 2/4 ?tsync 3/4 ?tsync tsync observation points jitter amount [tjp-p]
?32 CXA3106Q jitter peak-peak vs. output frequency output frequency [mhz] 20 90 40 60 1.0 2.5 3.0 3.5 jitter peak-peak [ns] 2.0 1.5 30 50 70 80 xga svga vga vga, n = 800, div = 1/2, cp = 10 svga, n = 1056, div = 1/2, cp = 10 xga, n = 1344, div = 1/1, cp = 10 k vco characteristics vrc2 control voltage [v] 2.0 4.5 2.5 3.0 3.5 4.0 0 50 100 150 200 output frequency [mhz] ta = ?5? ta = +25? ta = +75? k vco characteristics vrc2 control voltage [v] 2.0 4.5 2.5 3.0 3.5 4.0 0 50 100 150 200 clkih output frequency [mhz] div = 1/1 div = 1/2 div = 1/4 coarse delay td1 vs. coarse delay bit coarse delay bit 03 12 1 3 4 5 coarse delay td1 [clk] 2 ta = ?5? ta = +25? ta = +75? fine delay td2 vs. fine delay bit fine delay bit 020 51015 0 10 15 20 25 fine delay td2 [1/16 clk] 5 ta = ?5? ta = +25? ta = +75? example of representative characteristics
?33 CXA3106Q notes on operation be sure not to separate the analog and digital power supplies, and the analog and digital gnd. the ground pattern should be as wide as possible. using a multi-layer substrate with a mat ground is recommended. ground the power supply pins of the ic with a 0.1f or larger ceramic chip capacitor as close to each pin as possible. be sure to accurately match the i/o characteristic impedance in order to ensure sufficient performance during high-speed operation. design the set so that the loop filter (external) is located at the minimum distance. (see the CXA3106Q pwb.)
?34 CXA3106Q (1) recommended pecl i/o circuit the peripheral circuits mainly use pecl for digital input and output. of course, pecl and ttl can also be mixed. in this case, disable the ttl outputs with the control registers. * 3 gnd v cc (+5.0v) control register hold synch, syncl: pecl level complementary input 100pf 0.33f 3.3k w 1200pf loop filter * 4 1.6k w 100 w v cc unlock output * 2 gnd 100k w 10nf pecl level output pins 330 w gnd iov cc iognd vcoh vcol vco hold synch syncl sync senable sclk sdata peclv cc vbb dsynch dsyncl clkh clkl clk/2h clk/2l peclv cc iognd ttlv cc ttlgnd dsync clk clkn clk/2 clk/2n dgnd dv cc unlock divout serout cs tload iognd iov cc pllv cc pllgnd vcov cc vcognd vcohgnd iref rc2 rc1 irgnd irv cc 40 39 38 37 41 42 43 44 45 46 47 48 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 31 32 33 25 26 27 28 29 30 2 3 4 5 6 7 8 9 10 11 12 1 notes) * 1 unless otherwise specified, all capacitors are 0.1f. * 2 vary the external resistor and capacitor values of the unlock output as necessary. * 3 this external resistor (1.6k w ) should be a metal film resistor in consideration of temperature characteristics. * 4 the loop filter's capacitors and resistor should also be temperature compensated.
?35 CXA3106Q (2) recommended ttl i/o circuit the peripheral circuits mainly use ttl for digital input and output. of course, pecl and ttl can also be mixed. * 3 gnd v cc (+5.0v) control register hold sync: ttl level input 100pf 0.33f 3.3k w 1200pf loop filter * 4 1.6k w 100 w v cc unlock output * 2 gnd 100k w 10nf ttl level output pins iov cc iognd vcoh vcol vco hold synch syncl sync senable sclk sdata peclv cc vbb dsynch dsyncl clkh clkl clk/2h clk/2l peclv cc iognd ttlv cc ttlgnd dsync clk clkn clk/2 clk/2n dgnd dv cc unlock divout serout cs tload iognd iov cc pllv cc pllgnd vcov cc vcognd vcohgnd iref rc2 rc1 irgnd irv cc 40 39 38 37 41 42 43 44 45 46 47 48 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 31 32 33 25 26 27 28 29 30 2 3 4 5 6 7 8 9 10 11 12 1 notes) * 1 unless otherwise specified, all capacitors are 0.1f. * 2 vary the external resistor and capacitor values of the unlock output as necessary. * 3 this external resistor (1.6k w ) should be a metal film resistor in consideration of temperature characteristics. * 4 the loop filter's capacitors and resistor should also be temperature compensated.
?36 CXA3106Q connecting the CXA3106Q with sony adc (demultiplex mode) when connecting the pll output to a/d converters with built-in demultiplex function such as the cxa3026aq/cxa3026q/cxa3086q (sony), a simple system can be configured by connecting the clk (pecl) and clkn (pecl) outputs of the CXA3106Q to the clk (pecl) and clkn (pecl) inputs of each a/d converter, respectively, and the 1/2 clk (pecl) and 1/2 clkn (pecl) outputs of the CXA3106Q to the resetn (pecl) and reset (pecl) inputs of each a/d converter, respectively. (when the pll counter value n is an even number) wiring diagram 8 or 6 ttl 8 or 6 ttl vin clk (pecl) clkn (pecl) resetn (pecl) reset (pecl) adc cxa3026aq cxa3026q cxa3086q 8 or 6 ttl 8 or 6 ttl vin clk (pecl) clkn (pecl) resetn (pecl) reset (pecl) adc cxa3026aq cxa3026q cxa3086q 8 or 6 ttl 8 or 6 ttl vin clk (pecl) clkn (pecl) resetn (pecl) reset (pecl) adc cxa3026aq cxa3026q cxa3086q cmos logic clk (ttl) reset (ttl) dsync (ttl) 1/2 clkn (pecl) 1/2 clk (pecl) clkn (pecl) clk (pecl) pll CXA3106Q ?cxa3026aq 8bit 140msps adc ?cxa3026q 8bit 120msps adc ?cxa3086q 6bit 140msps adc r g b 1/2 clk (ttl)
?37 CXA3106Q CXA3106Q and sony adc (demultiplex mode) timing the CXA3106Q and cxa3026q/cxa3026aq/cxa3086q timings are shown below. here, the important timings are as follows. (the clock cycle is labeled as t.) within the a/d converters clock input vs. reset input the setup time is t?ns and the hold time is 0ns, satisfying the a/d converter specifications. within the cmos logic at the rear end of the a/d converters a/d converter data output vs. 1/2 clock output timing the setup time is t?.5ns and the hold time is t?.5ns. (these timings also include combinations of three a/d converters from different lots, and are defined for all operating temperatures and all operating supply voltages. see the cxa3026q/cxa3026aq/cxa3086q specifications for a detailed description.) within the cmos logic at the rear end of the a/d converters dsync signal from CXA3106Q vs. a/d converter 1/2 clock output the setup time is t?ns and the hold time is t?ns. clk (pecl) out t 3 to 7.5ns 0 to 1ns 4.5 to 8ns thold min. t?ns tsetup min. t?ns tsetup min. t?.5ns thold min. t?.5ns dsync (ttl) out 1/2clk (pecl) out 1/2clk (ttl) out data (ttl) out cxa3026q cxa3026aq cxa3086q CXA3106Q * see the cxa3026aq/q and cxa3086q specifications.
?38 CXA3106Q connecting the CXA3106Q with sony adc (straight mode) when connecting the pll output to a/d converters such as the cxa3026aq/cxa3026q/cxa3086q (sony), a simple system can be configured as shown below. wiring diagram 8 or 6 ttl vin clk (pecl) clkn (pecl) adc cxa3026aq cxa3026q cxa3086q 8 or 6 ttl vin clk (pecl) clkn (pecl) adc cxa3026aq cxa3026q cxa3086q 8 or 6 ttl vin clk (pecl) clkn (pecl) adc cxa3026aq cxa3026q cxa3086q cmos logic clk (ttl) reset (ttl) dsync (ttl) clk (ttl) clkn (pecl) clk (pecl) pll CXA3106Q ?cxa3026aq 8bit 140msps adc ?cxa3026q 8bit 120msps adc ?cxa3086q 6bit 140msps adc r g b
?39 CXA3106Q CXA3106Q and sony adc (straight mode) timing the CXA3106Q and cxa3026q/cxa3026aq/cxa3086q timings are shown below. here, the important timings are as follows. (the clock cycle is labeled as t.) within the cmos logic at the rear end of the a/d converters a/d converter data output vs. clock output from CXA3106Q the setup time is t?.5ns and the hold time is 2ns. (these timings also include combinations of three a/d converters from different lots, and are defined for all operating temperatures and all operating supply voltages. see the cxa3026q/cxa3026aq/cxa3086q specifications for a detailed description.) within the cmos logic at the rear end of the a/d converters dsync signal from CXA3106Q vs. clock output from CXA3106Q the setup time is t?.5ns and the hold time is 1.5ns. clk (pecl) out t 1.5 to 4.5ns 1.5 to 3ns 6.5ns min thold min. 2ns clk (ttl) out dsync (ttl) out data (ttl) out cxa3026q cxa3026aq cxa3086q CXA3106Q tsetup min. t?.5ns tsetup min. t?.5ns thold min. 1.5ns 10ns max
?40 CXA3106Q CXA3106Q-pwb (CXA3106Q evaluation board) the CXA3106Q-pwb is an evaluation board for the CXA3106Q pll-ic. this board makes it possible to easily evaluate the CXA3106Q's performance using the supplied control program (note: ibm pc/at, ms-dos 5.0 and newer us mode specifications). features two input level (ttl and pecl) sync input two output level (ttl and pecl) clk, clk2 and dsync output supply voltage: +5.0v absolute maximum ratings (ta = 25?) supply voltage v cc ?.5 to +7.0 v recommended operating conditions supply voltage v cc 4.75 to 5.25 v gnd 0 v digital input (pecl) din (high) v cc ?1.1 v (min.) din (low) v cc ?1.5 v (max.) (ttl) din (high) gnd + 2.0 v (min.) din (low) gnd + 0.8 v (max.) operating ambient temperature ta ?0 to +75 ? block diagram vco input (pecl/ttl) CXA3106Q 48pin qfp 3 loop filter sync input (pecl/ttl) control bus (ttl) senable, sclk, sdata dsync output (pecl/ttl) clk output (pecl/ttl) clk/2 output (pecl/ttl) vbb (pecl) serout (ttl) divout (ttl) unlock (ttl)
?41 CXA3106Q setting methods and notes on operation input pins this pwb supports ttl single and pecl complementary input. input pins: sync: ttl level input, 10 to 100khz syncl: pecl low level input, 10 to 100khz synch: pecl high level input, 10 to 100khz vco: ttl level input. this is a test pin and is therefore normally not used. vcol: pecl low level input. this is a test pin and is therefore normally not used. vcoh: pecl high level input. this is a test pin and is therefore normally not used. output pins this pwb supports ttl single and pecl complementary output. dsynch, dsyncl: pecl level complementary delay sync outputs. the output range is 10 to 100khz. dsync: ttl level delay sync output. the output range is 10 to 100khz. clkh, clkl: pecl level complementary clk outputs. the output range is 10 to 120mhz. clk, clkn: ttl level complementary clk outputs. the output range is 10 to 80mhz. clk/2h, clk/2l: pecl level complementary 1/2 clk outputs. the output range is 5 to 60mhz. clk/2, clk/2n: ttl level complementary clk outputs. the output range is 5 to 60mhz. vbb: outputs the pecl amplitude threshold voltage. serout: ttl level control register serial data output. divout: ttl level internal programmable counter test output. unlock: ttl level unlock output. this pin requires external circuits such as appropriate capacitors and resistors. see the ic specifications for a detailed description. pecl outputs (vbb, dsynch, dsyncl, clkh, clkl, clk/2h, clk/2l) are output constantly, but ttl outputs (dsync, clk, clkn, clk/2, clk/2n, serout, divout, unlock) are controlled by the respective control registers. therefore, the enable/disable settings should be made in accordance with the application. see the following pages for the setting method.
?42 CXA3106Q jumper wire settings s1, s2: these enable/disable hold (pin 6). hold is active high, so the jumper wire should be connected to s2 (hold = low) for normal use. when using hold, connect the jumper wire to s1 (hold = high). (for the initial setting, the jumper wire is connected to s2.) s3, s4: these enable/disable tload (pin 13). connect the jumper wire to s4 (tload = high) for normal use. when using tload, connect the jumper wire to s3 (tload = low). (for the initial setting, the jumper wire is connected to s4.) s5, s6: these enable/disable cs (pin 14). connect the jumper wire to s6 (cs = high) for normal use. when using power save, connect the jumper wire to s5 (cs = low). (for the initial setting, the jumper wire is connected to s6.) supplied program this pwb is equipped with a control program that facilitates evaluation of the CXA3106Q. operation methods and precautions are as follows. 1) compatible personal computers use an ibm pc/at or compatible machine equipped with a 25-pin d-sub parallel port (printer port). also, operating systems which support the program are ms-dos 5.0 or newer and ms-windows 3.1 or newer. (when using windows, start the program from the dos window.) 2) connect the supplied cable connect the supplied cable to the parallel port of the personal computer and the dbus1 connector of the CXA3106Q-pwb. 113 14 25 d-sub 25-pin parallel connector pin arrangement 2pin : sclk 3pin : sdata 4pin : senable 11pin : serin 19pin : gnd 3) connect the power cable and supply power to the CXA3106Q-pwb 4) start the program a) boot the personal computer and then shift to the directory containing the program. b) set ms-dos to us mode. ? us return or enter c) input the program name. ? * 1 cxa3106a or cxa3106b return or enter ? move to the program screen. * 1 only one of either cxa3106a or cxa3106b can be used as the program name depending on the printer port setting of the personal computer.
?43 CXA3106Q 5) description of the program screen a) when the program is started, the following initial screen is displayed. please type the name of the initialization file or press enter. the file extention.ini should not be included. the default file when enter is pressed is cxa3106.ini filename > _ when this screen appears, press the return or enter key. the screen shifts to the function setting screen. b) function settings when the program is loaded, the following function setting screen appears. cxa3106 pll registers divisor 1344 divider 2 coarse delay 00 fine delay 10 charge pump 10 polarity power sync dsync pd scan synth vco bypass 1 1 1 off on on o/p enable divout unlock dsync clk2 nclk2 clk1 nclk1 off off off off off off off use arrow keys to select data bit. press enter to toggle and load data. use pg up and pg dn to increment/decrement divisor and fine delay registers. press a to abort, s to scan registers mixed signal systems jan 1997
?44 CXA3106Q divisor this is used to input the frequency division ratio of the program counter. the value can be changed as desired from 9 to 4111 by moving the cursor to the position of the number and pressing the return or enter key. (note: the operating range of the CXA3106Q is from 256 to 4096.) the value can also be incremented or decremented by one step by pressing the page up or page down key, respectively. the internal vco has an oscillator frequency of 40 to 120mhz, so the output frequency and divider (vco frequency divider) setting range are as follows. 40 120 20 60 10 30 divider = 1 divider = 2 divider = 4 40 80 120 1/4 1/2 1/1 o/p frequency [mhz] divider divider this sets the vco output frequency division ratio to 1/1, 1/2 or 1/4. the frequency division ratio changes repeatedly in the order of 1/1 ? 1/2 ? 1/4 ? 1/1 each time the cursor is moved to the position of the number and the return or enter key is pressed. coarse delay this is the dsync upper delay time setting. the value can be changed by moving the cursor to the position of the number and pressing the return or enter key. the delay time variable range settings are "00" (1 clk), "01" (2 clk), "10" (3 clk) or "11" (4 clk). fine delay this is the dsync lower delay time setting. the value can be changed by moving the cursor to the position of the number and pressing the return or enter key. the value can also be incremented or decremented by one step by pressing the page up or page down key, respectively. the delay time can be varied from 1/16 clk to 32/16 clk by setting "0" to "31", respectively. charge pump this is the charge pump circuit ki setting. the value can be changed by moving the cursor to the position of the number and pressing the return or enter key. ki can be set to "00" (about 100a), "10" (about 400a) or "11" (about 1.6ma). the setting "01" is not used. (setting "01" is the same as setting "00".) polarity these are the sync, dsync and pd (phase detector) polarity inversion settings, and should be set as necessary such as when inverting the sync input and dsync output waveforms. the setting value "1" is positive polarity, and "0" is negative polarity. these should normally all be set to "1". (fix pd to "1" other than during test mode.)
?45 CXA3106Q power scan: this is the control register read setting. when this is on, the control register serial data is output from serout (pin 15). this should normally be set to off. synth: this is the enable/disable setting for this ic. this should normally be set to on. vco bypass: this is set to off when testing the program counter. this should normally be set to on. o/p enable these are the enable/disable settings for each ttl output (divout, unlock, dsync, clk2, nclk2, clk1 and nclk1). set to on when performing evaluation using ttl output.
?46 CXA3106Q scan result, cxa3106 pll registers register 1 divreg1 00111000 register 2 divreg2 0101 register 3 cenfrereg 1011111 register 4 delayreg 0010000 register 5 cpreg 100 register 6 ttlpolreg 00000011 register 7 testpowreg 0111 press r to return to pll registers menu. press a to abort mixed signal systems aug 1996 c) description of readout mode this program has a function (readout mode) that reads the contents written to the control registers from the CXA3106Q serout (pin 15) and displays these contents on the screen. this function is described below. 1) set scan to on at the function setting screen. 2) press the s key. the following screen appears. this screen conforms to the control register table listed in the CXA3106Q specifications. 3) press the r key to return to the original function setting screen. d) quit the program press the a key to quit the program.
?47 CXA3106Q substrate pattern (parts surface) substrate pattern (solder surface) aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aa aa aa aa aaaa aaaa aaaaa aaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa a
?48 CXA3106Q silk screen (parts surface) silk screen (solder surface) c1 c14 c18 c17 c13 c15 c16 c10 c9 c8 c12 c19 c20 c11 c7 c3 c2 c4 c6 c18 c5 vco bnc3 vcol bnc2 vcoh bnc1 vcc synch bnc4 syncl bnc5 sync bnc6 s1 s2 r19 ic1 s3 s4 s5 s6 pr2 serout pr3 divout pr4 unlock pr11 clk/2n pr12 clk/2 pr13 clkn pr14 clk pr15 dsync pr1 clk/2l pr5 clk/2h r6 r13 r5 r12 pr6 clkl pr7 clkh r7 r14 r4 r11 pr8 dsyncl pr9 dsynch r3 r10 r2 r9 pr10 vbb r1 r8 c21 33 + CXA3106Q pcb v1.1 dbus1 control register gnd
?49 CXA3106Q pwb circuit diagram s1 s2 c2 0.1 c3 0.1 c19 0.33 c20 1200p r18 3.3k gnd r19 1.6k c11 100p c4 0.1 c5 0.1 c6 0.1 c12 0.1 c7 0.1 s3 s4 s5 s6 c9 0.1 gnd gnd c8 0.1 c10 0.1 v cc r8 330 r1 r9 330 r2 r10 330 r3 r11 330 r4 r14 330 r7 r12 330 r5 r13 330 r6 v cc pr10a vbb pr9a dsynch pr8a dsyncl pr7a clkh pr6a clkl pr5a clk/2h pr1a clk/2l pr15a dsync pr14a clk pr13a clkn pr12a clk/2 pr11a clk/2n c1 0.1 c13 0.1 c14 0.1 c15 0.1 c18 0.1 c16 0.1 c17 0.1 gnd v cc c21 33 pwr1 v cc pwr2 gnd pr3a divout pr4a unlock pr2a serout 1 5 dbus1 control register gnd bnc6 sync bnc5 syncl bnc4 synch bnc3 vco bnc2 vcol bnc1 vcoh iognd iov cc pllv cc pllgnd vcov cc vcognd vcohgnd iref rc2 rc1 irgnd irv cc 40 39 38 37 41 42 43 44 45 46 47 48 dsync clk clkn clk/2 clk/2n dgnd dv cc unlock divout serout cs tload 13 14 15 16 17 18 19 20 21 22 23 24 peclv cc vbb dsynch dsyncl clkh clkl clk/2h clk/2l peclv cc iognd ttlv cc ttlgnd 36 35 34 31 32 33 25 26 27 28 29 30 iov cc iognd vcoh vcol vco hold synch syncl sync senable sclk sdata 2 3 4 5 6 7 8 9 10 11 12 1 CXA3106Q note) r1 to r7 are not mounted.
?50 CXA3106Q package outline unit: mm sony code eiaj code jedec code m package structure package material lead treatment lead material package weight epoxy resin solder / palladium plating copper / 42 alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.12 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 0.15 ?0.05 + 0.1 qfp-48p-l04 * qfp048-p-1212-b 0.7g note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame).

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